High Performance Energy Efficient CMOS Voltage Level Shifter Design

Abstract

This paper presents an energy efficient voltage CMOS voltage level shifter. Voltage level shifter is used for multi-supply design applications. The main purpose of voltage level shifter is to convert the voltage level from one level to another. We verified our voltage level shifter in ASAP7 7nm Fin-Fet technology. The proposed voltage level shifter is based on differential cascade voltage switch logic, which takes an input voltage in the range of 0.25V to 0.6V and provides an output of 0.7V. Our voltage level shifter improves propagation delay and power dissipation with 48% and 43%, respectively, with recently reported Wilson current mirror voltage level shifter with Zero-Vth design. The proposed design technique comes up with significantly lower power consumption and drastically reduced propagation delay over a wide range of temperatures (-25 to 25 degree Celsius), as compared to existing technologies.