FPGA based Histogram Equalization for Image Processing

Abstract

Histogram Equalization is one of the most common algorithms used in image processing applications. Traditional software based histogram equalization using CPU is no longer sufficient for high-computation based real-time image processing applications. To meet high computation demand, image processing operations can be hardware accelerated using Field Programmable Gate Array (FPGA). In this paper, we implemented histogram equalization using Verilog Hardware Description Language (HDL) on Xilinx FPGA for hardware acceleration. The result shows that our FPGA-based histogram equalization is on average 1.5 thousand times faster than traditional software based histogram equalization on CPU.