3 GHz CMOS Doherty power amplifier for high efficiency

2017 Seminar on Detection Systems Architectures and Technologies (DAT) Pub Date : 1900-01-01 DOI:10.1109/DAT.2017.7889155

S. Traiche, A. Slimane

引用次数: 6

Abstract

This paper presents a design of 3 GHz CMOS fully integrated Doherty power amplifier (DPA). The proposed DPA design is composed of two parallel amplifier stages, the principal in class AB and the auxiliary in class B. Both DPA stages use a cascode topology for its high output-input isolation, and high supply voltage possibility. Based on 0.13-µm CMOS process and supplied by 2.6 V of supply voltage, the simulation results of the proposed DPA shows 17 dB of power gain and a maximal output power of 26 dBm, and 37% of power added efficiency for the 6 dB back-off point and 48 % for the maximal output power.

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3 GHz CMOS Doherty功率放大器，效率高

本文设计了一种3ghz CMOS全集成Doherty功率放大器(DPA)。所提出的DPA设计由两个并联放大器级组成，主级为AB级，辅助级为b级。两个DPA级均采用级联编码拓扑，以实现高输出输入隔离和高供电电压可能性。基于0.13µm CMOS工艺，在2.6 V电源电压下，仿真结果表明，该DPA的功率增益为17 dB，最大输出功率为26 dBm，在6 dB的后退点时功率增加效率为37%，最大输出功率增加效率为48%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2017 Seminar on Detection Systems Architectures and Technologies (DAT)

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