Polysilicon thin film transistors with field-plate-induced drain junction for both high-voltage and low-voltage applications

Abstract

Polysilicon low-voltage (LV) and high-voltage (HV) thin-film transistors (TFTs) required in high-performance large-area devices, such as printers and LCD displays, are considered. The authors (1990) proposed an improved HVTFT device structure with an independently-biased metal field plate (FP) overlapping the entire offset region. The new FP-HVTFT eliminates the expensive lightly-doped-drain implant required in the conventional offset-gate HVTFTs and the current-pinching effects commonly observed in conventional offset-gate polysilicon HVTFTs. The authors report the effects of offset length (L/sub off/) on the new FP-HVTFTs, as the device characteristics of the conventional offset-gate polysilicon HVTFTs are known to be very sensitive to L/sub off/, and L/sub off/ is set by the alignment between two masking layers in actual device fabrication. The feasibility is reported of using the field-plate device as a low-voltage TFT for reducing the off-state leakage current.<>