4 Bit and 8 Bit Convolution Using Vedic Multiplier

Abstract

One of the fundamental processes in digital signal processing is convolution. The mathematical process of mixing two signals to create a third signal is called convolution. Utilizing a Vedic multiplier, Urdhava Triyagbhyam Sutra or UT sutra, based on one of the sixteen Vedic mathematics sutras, linear and circular convolution processing is accelerated. The Urdhava Triyagbhyam multiplier compared to other traditional multipliers offers faster results. Multiplier having pipelining architecture is also used to compute the convolution (circular and linear) of two sequences because it speeds up the multiplication process. Xilinx ISE Design suite 14.7 software is used to carry out the simulation and synthesis using VHDL. The area and delay for 4 bit and 8 bit circular and linear convolution is computed.