Linearity characterization of nano-scale underlap SOI MOSFETs

I. V. Singh, M. S. Alam
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Abstract

This work presents the linearity characterization by varying the process parameters of new underlap Silicon-on-Insulator (SOI) MOSFETs (with high-k stack on spacer) in single gate (SG) and double gate (DG) configurations. Using linearity defined in-terms of third order intercept (IP3), the paper presents guideline for optimum value of spacer “s”, film thickness “Tsi”and doping gradient “d” to maximize the linearity of new underlap design. Based on a new Figure-of-Merit (FoM) involving intrinsic gain Av, IP3, maximum oscillation frequency fMAX and dc power consumption PDC, it has been found that FoM in DG configuration is almost three times higher than that of SG design. This is due to a combination of higher value of fMAX, Av and IP3 in DG configuration with power consumption of ~ 2.1 mW. The higher value of FoM in DG device has been achieved at similar “on” to “off” current ratio (Ion/Ioff) as specified in current International Technology Road map for Semiconductors (ITRS).
奈米搭接SOI mosfet的线性特性
本研究通过改变单栅极(SG)和双栅极(DG)配置下新型绝缘体上硅(SOI) mosfet(在间隔层上具有高k堆叠)的工艺参数,提出了线性特性。利用三阶截距(IP3)定义的线性度,本文给出了间隔层s、膜厚Tsi和掺杂梯度d的最佳值准则,以最大限度地提高新underlap设计的线性度。基于一种包含固有增益Av、IP3、最大振荡频率fMAX和直流功耗PDC的新型性能图(FoM),发现DG结构的FoM几乎比SG设计的FoM高3倍。这是由于DG配置中fMAX、Av和IP3值较高,功耗约为2.1 mW。DG器件中更高的FoM值是在当前国际半导体技术路线图(ITRS)中规定的类似“通”与“关”电流比(Ion/Ioff)下实现的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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