Efficient pattern-based emulation for IEEE 802.11a baseband

Il-Gu Lee, Heejung Yu, Sok-Kyu Lee, Jin Lee, Sin-Chong Park
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引用次数: 0

Abstract

As the design complexity and the number of gates per pin are increasing rapidly, functional verification has become a critical step in the development of a system-on-chip (SoC). Traditional verification techniques, such as simulation or emulation, cannot satisfy the debugging requirement and simulation speed. Among various verification technologies, pattern-based emulation provides the most efficient execution speed, but has limited observability due to the limit on the number of available pins and memory size. In addition, it takes a long time to dump patterns into memory. We propose an efficient pattern-based emulation approach that combines a cycle-based simulation, an input pattern reduction method based on coverage result, and an automatic pattern comparing scheme.
IEEE 802.11a基带的高效基于模式的仿真
随着设计复杂性和每引脚门数的迅速增加,功能验证已成为系统级芯片(SoC)开发的关键步骤。传统的仿真、仿真等验证技术已不能满足调试要求和仿真速度。在各种验证技术中,基于模式的仿真提供了最有效的执行速度,但由于可用引脚数量和内存大小的限制,其可观察性受到限制。此外,将模式转储到内存中需要很长时间。我们提出了一种有效的基于模式的仿真方法,该方法结合了基于周期的仿真、基于覆盖结果的输入模式缩减方法和自动模式比较方案。
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