Il-Gu Lee, Heejung Yu, Sok-Kyu Lee, Jin Lee, Sin-Chong Park
{"title":"Efficient pattern-based emulation for IEEE 802.11a baseband","authors":"Il-Gu Lee, Heejung Yu, Sok-Kyu Lee, Jin Lee, Sin-Chong Park","doi":"10.1109/IWSOC.2005.55","DOIUrl":null,"url":null,"abstract":"As the design complexity and the number of gates per pin are increasing rapidly, functional verification has become a critical step in the development of a system-on-chip (SoC). Traditional verification techniques, such as simulation or emulation, cannot satisfy the debugging requirement and simulation speed. Among various verification technologies, pattern-based emulation provides the most efficient execution speed, but has limited observability due to the limit on the number of available pins and memory size. In addition, it takes a long time to dump patterns into memory. We propose an efficient pattern-based emulation approach that combines a cycle-based simulation, an input pattern reduction method based on coverage result, and an automatic pattern comparing scheme.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWSOC.2005.55","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
As the design complexity and the number of gates per pin are increasing rapidly, functional verification has become a critical step in the development of a system-on-chip (SoC). Traditional verification techniques, such as simulation or emulation, cannot satisfy the debugging requirement and simulation speed. Among various verification technologies, pattern-based emulation provides the most efficient execution speed, but has limited observability due to the limit on the number of available pins and memory size. In addition, it takes a long time to dump patterns into memory. We propose an efficient pattern-based emulation approach that combines a cycle-based simulation, an input pattern reduction method based on coverage result, and an automatic pattern comparing scheme.