ION/IOFF Improvement for No Junction Surrounding Gate TFET with different high-k values

Abstract

The research paper recounts about the 3-D nanodevice, Junctionless Surrounding gate Tunnel FET. The proposed structure is simulated using a TCAD device simulator. The electrical parameters like Surface Potential, Electric Field, Drain current, Transconductance were analyzed. The proposed structure was simulated to implement and analyze the characteristics of stacked oxide layer. Comparing the results of device Transverse characteristics for Junction and Devoid of Junction, the outperformance of Junctionless Surrounding gate Tunnel FET was obtained.