Assertion based verification of PSL for SystemC designs

Abstract

In this paper, we present an assertion based verification approach for SystemC designs, based on embedding the property specification language (PSL) using abstract state machines (ASM). Our approach utilizes an existing embedding of PSL in ASM in order to enable modeling of PSL assertions at the ASM level. Here, we propose to compile PSL assertions into C# code, and integrate them with the SystemC design. Assertions are then verified by simulating the new model that combines the original design and the integrated assertions. This enriches the SystemC language with a powerful and expressive assertion specification layer, and improves the verification of SystemC designs by targeting specific properties during simulation.