FSNoC: Safe Network-on-Chip Design with Packet Level Lock Stepping

Abstract

Functional safety is the top priority for the design of automotive and other mission-critical systems. We proposed Functional Safe NoC (FSNoC) with a new Packet Level Lock Stepping (PLLS) concept for Concurrent Error Detection (CED) of Network-on-Chip (NoC) with high Diagnostic Coverage (DC) and reduced area overhead. Furthermore, we proposed to divide the NoC network of a System-On-Chip(SOC) design into partitions with different performance requirements and apply separate but inter-operable safety mechanisms based on Performance Power Area (PPA) trade-off given the design meet safety requirement. The proposed techniques were used on an industry NoC design to achieve over 99% DC coverage with 11–33% of area, 12–29% power overhead and 5–22% of wiring overhead depending on partition choices.