A new technique for imaging the logic state of passivated conductors: biased resistive contrast imaging (CMOS devices)

Abstract

A scanning electron microscopy imaging technique to examine the voltage level of conductors on passivated CMOS integrated circuits is discussed. Biased resistive contrast imaging uses a modified resistive contrast imaging system to acquire image data on powered circuits. The image is generated by monitoring small fluctuations in the power supply current of an integrated circuit as an electron beam is scanned over the circuit surface. The images resemble voltage contrast data from circuits with the passivation removed and the surface topography subtracted. Nondestructive applications of this imaging method to functional and failed integrated circuits are described. Possible irradiation effects and methods to minimize them are also discussed.<>