An upper limit for aggregate I/O interconnect bandwidth of GSI chips constrained by power dissipation

Abstract

For the first time, the average energy dissipation per input/output bits is estimated, which is very useful in determining an upper bound for chip aggregate I/O bandwidth for a given dynamic power budget. Some empirical parameters such as Rent's parameters and activity factor are used to capture the impact of chip architecture. For a projected multiprocessor implemented at the 45 nm technology node it is shown that 30 Tb/s is the maximum aggregate I/O bandwidth for 100W dynamic power dissipation.