Implementation of a window-based scheduler in an ATM switch

Abstract

ATM networks have to handle a wide range of traffic characteristics and performance requirements. The transmission control scheme should regulate the flow of packets from the switching queues to the outgoing links. The quality of service (QoS) requirements can be provided by delivering the cell within a maximum predetermined delay and without exceeding the maximum limit of allowable cell loss. We propose a switching scheme to satisfy different QoS requirements. The basic buffering component of the switch is a virtual dual-ported memory shared by all input and output lines. Cells arriving on input lines are stored to the common memory. The memory is divided into multiple priority queues to handle different classes of services. Cells are simultaneously retrieved from the priority queues and transmitted over the output lines. The higher priority queues can send a predefined number of cells before the lower priority queues are serviced in order to maintain the Qos of each class. The architecture of the switch is described. A simulation for the switch is run to show the effect of the scheduling protocol on the performance metrics.