Implementation of ECG Classification Xilinx System Generator

Abstract

this paper presents a method to implement an Electrocardiogram (ECG)-neuro classifier on FPGA kit using Xilinx System Generator blocks. An approximate linear phase bi-reciprocal lattice wave digital filter (BLWDF) is used for QRS complex extraction. The output of the BLWDF is fed into a neuro classifier system. Various ECG signals from the European ST-T and QT databases are then classified into four classes of human heart diseases: Normal, Right Bundle Branch Block (RBBB), Left Ventricular Hypertrophy (LVH), Left Bundle Branch Block (LBBB). Neural network training process is accomplished using Matlab toolbox to obtain the weights and bias values. The classifier is then implemented on a Spartan6 Xilinx Field Programmable Gate Array (FPGA) device. A feed forward neural network with two layers and four neurons with an activation function of the type "tan-sigmoid" is modeled using Xilinx System Generator blocks. The models are then translated into Very High Speed IC Hardware Description Language (VHDL) to measure the usage percentage of the chip resources and to calculate the maximum operating frequency.