Synthesis & Testing for Low Power

A. Pal, S. Chattopadhyay
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Abstract

In recent years, power dissipation has emerged as the key issue not only for portable computers and mobile communication devices, but also for high-end systems. Reducing power dissipation is of primary importance in achieving longer battery life in portable devices. On the other hand, for high-end systems the cooling and packaging requirements are pushing the chip designers for low power alternatives. As a consequence, apart from the size, cost and performance, now-adays power is also considered as one of the most important constraints. This has led to vigorous research in the synthesis of low-power and high-performance circuits and systems. Moreover, aggressive device size scaling used to achieve high-performance leads to increased variability due to short-channel and other effects. This, in turn, leads to variations in process parameters such as, Leff, Nch, W, Tox, Vt, etc. Performance parameters such as power and delay are significantly affected due to the variations in process parameters and environmental/operational (Vdd, temperature, input values, etc.) conditions. Due to variability, the design methodology in the future nanometer VLSI circuits will essentially require a paradigm shift from deterministic to probabilistic and statistical design approach. The tight constraint on power dissipation has also created new challenges for testing low power VLSI circuits, as the traditional test techniques do not account for power dissipation during test application. It is now an accepted truth that test power is often much higher than the power consumed in normal operation, due to voluminous test data, test parallelization and the low correlation between successive test patterns. The objective of this tutorial is to provide an overview of different aspects of low power circuit synthesis at various levels of design hierarchy. It will introduce techniques to optimize the performance and power in the presence of process variations. Low power testing techniques will also be discussed.
低功耗合成与测试
近年来,功耗不仅成为便携式计算机和移动通信设备的关键问题,而且成为高端系统的关键问题。在便携式设备中,降低功耗对于延长电池寿命至关重要。另一方面,对于高端系统,冷却和封装要求正在推动芯片设计师寻找低功耗替代品。因此,除了尺寸、成本和性能之外,如今功率也被认为是最重要的限制之一。这导致了对低功耗和高性能电路和系统的合成的蓬勃研究。此外,用于实现高性能的激进器件尺寸缩放导致由于短通道和其他影响而增加的可变性。这反过来又导致工艺参数的变化,例如,Leff, Nch, W, Tox, Vt等。由于工艺参数和环境/操作(Vdd、温度、输入值等)条件的变化,功率和延迟等性能参数受到显著影响。由于可变性,未来纳米级VLSI电路的设计方法将本质上需要从确定性到概率和统计设计方法的范式转变。对功耗的严格限制也给测试低功耗VLSI电路带来了新的挑战,因为传统的测试技术在测试应用过程中没有考虑到功耗。由于大量的测试数据、测试并行化和连续测试模式之间的低相关性,测试功率通常比正常运行时消耗的功率高得多,这是一个公认的事实。本教程的目的是在设计层次的不同层次上提供低功耗电路合成的不同方面的概述。它将介绍在存在工艺变化的情况下优化性能和功率的技术。低功耗测试技术也将被讨论。
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