{"title":"Configurable multi-layer CNN-UM emulator on FPGA","authors":"Z. Nagy, P. Szolgay","doi":"10.1109/CNNA.2002.1035049","DOIUrl":null,"url":null,"abstract":"A new emulated digital multi-layer CNN-UM chip architecture called Falcon has been developed. In this paper the main steps of the FPGA implementation are introduced. Main results are as follows: CNN-UM architecture emulated on Xilinx Virtex series FPGA, 3D non-linear spatio-temporal dynamics can be implemented on this architecture. The critical parameters of the implementation in single layer configuration are 55 million cell update/second/processor core or equivalently 1 GOPS computing performance. In face of the high performance the power requirements of the architecture are relatively low only /spl sim/3 W per processor core. Using re-configurable devices to implement emulated digital architectures provides more flexibility compared to the custom VLSI designs because different Falcon architectures can be used on the same FPGA device.","PeriodicalId":387716,"journal":{"name":"Proceedings of the 2002 7th IEEE International Workshop on Cellular Neural Networks and Their Applications","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2002-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"77","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2002 7th IEEE International Workshop on Cellular Neural Networks and Their Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CNNA.2002.1035049","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 77
Abstract
A new emulated digital multi-layer CNN-UM chip architecture called Falcon has been developed. In this paper the main steps of the FPGA implementation are introduced. Main results are as follows: CNN-UM architecture emulated on Xilinx Virtex series FPGA, 3D non-linear spatio-temporal dynamics can be implemented on this architecture. The critical parameters of the implementation in single layer configuration are 55 million cell update/second/processor core or equivalently 1 GOPS computing performance. In face of the high performance the power requirements of the architecture are relatively low only /spl sim/3 W per processor core. Using re-configurable devices to implement emulated digital architectures provides more flexibility compared to the custom VLSI designs because different Falcon architectures can be used on the same FPGA device.