Characterization of a pseudo-DRAM Crossbar Computational Memory Array in 55nm CMOS : (Invited Paper)

Abstract

As computational needs increase in relation to the growing fields of Internet of Things and Deep Learning, energy-efficient, computational units are needed to bypass DSP units within Von Neumann architectures. A charge-mode vector matrix multiplier (VMM) with compute-in memory capabilities was fabricated in the Global Foundries 55nm LP process. The array is comprised of a 156 row by 512 column crossbar where each row computes a 512 element binary dot product in the charge domain. This normalized analog multiply and accumulate (MAC) is carried out by charge-injection devices who compute a 1-bit multiplication in the charge domain. Preliminary test results show successful, linear output computation in the analog domain to various input vectors that are both digital and multi-level analog. The 156 × 512 compute-in memory, CID array has been simulated to achieve an efficiency of 1.8 TOPs per mW.