A 0.13 μm Low-power Race-free Programmable Logic Array

Abstract

A PLA using NAND and NOR gates for the AND and OR logic planes, respectively, is described. The circuit design, timing and power advantages are described. Nearly 50% power savings over a conventional PLA design is achieved on a 130 nm process at less than 10% delay cost. The new PLA circuit has been fabricated on a 130 nm low standby power process and tested silicon operates at 905 MHz at VDD = 1.5 V