Direct-Write 3D Printing of Interconnects for Fan-Out Wafer-Level Packaging

Abstract

Fan-out wafer-level packaging (FOWLP) is commonly used for manufacturing system-in-package components and multi-chip modules, where multiple integrated circuit dice can be combined in a common, compression-molded epoxy substrate with integrated interconnects and redistribution layers. While highly cost efficient at scale, this approach requires fixed tooling and metallization masks that limit its use for just-in-time configuration or rapid prototyping. In this work, we demonstrate the use of high-resolution 3D-printing for direct-write fabrication of electrical interconnects in conjunction with FOWLP processing. This approach enables both pre-mold deposition, for interconnects embedded in the epoxy substrate, and post-mold deposition, for interconnects fabricated monolithically on the substrate surface. Here, we demonstrate process development and electrical characterization of printed interconnects, along with both pre- and post-mold printed interconnect structures and fan-out for embedded, bare IC dice.