Area-Per-Yield and Defect Level of Cascaded TMR for Pipelined Processors

Abstract

In this paper we evaluate the effectiveness of cascaded triple modular redundancy (TMR) in terms of area-per-yield and defect level by applying to every stage of a pipelined processor. Considering a cascade of nine possible TMR stage architectures, we theoretically derive the area-per-yield on the basis of the given parameters of defect density and the number of stages. Also, assuming that a production test is independently applied for each module and voter in every stage and the pass/fail of a chip is determined on the basis of the test result, we theoretically derive the defect level for the given fault coverage. Numerical examples show that the application of cascaded TMR improves the area-per-yield and the defect level when manufacturing yield is low. In addition, some cases exist in which the number of stages minimize the area-per-yield or the defect level.