NTX: A 260 Gflop/sW Streaming Accelerator for Oblivious Floating-Point Algorithms in 22 nm FD-SOI

Abstract

In this work we present the first complete design, silicon implementation and measurements in 22 nm FD-SOI of the Network Training Accelerator (NTX) architectural concept [1]. NTX is based on a newly designed partial carrysave "wide-inside" (300 bit) fused multiply-accumulate (FMAC) unit ensuring IEEE 754 compliance and a Root Mean Squared Error 1.7_lower than a conventional 32 bit FPU on long accumulations such as dot products and convolutions.