Mitigating Drain Source Voltage Oscillation with Low Switching Losses for SiC Power MOSFETs Using FPGA-Controlled Active Gate Driver

Abstract

In order to improve the switching performance of SiC MOSFETs at turn-off, the drain-source voltage oscillation should be mitigated with low switching losses. To achieve this improvement, an approach, which uses an FPGA-controlled active gate driver with two level switchable gate resistances, is investigated and presented in this paper. To ensure the performance of this approach for varying operating points in a wide range, three methods are shown and compared to find the best solution.