{"title":"A 21.2-23-GHz Ultra-Low-Power Injection-Locked Frequency Tripler Using Current-Reuse Structure","authors":"Xiaoying Deng, Linsen Xie","doi":"10.1109/ICCS52645.2021.9697180","DOIUrl":null,"url":null,"abstract":"In this paper, an ultra-low-power injection-locked frequency tripler (ILFT) based on a current-reuse structure is proposed with SMIC 55-nm CMOS design kit. Different from the conventional structure with a cross-coupling pair of two NMOS transistors, a current-reuse structure is introduced, consisting of a single PMOS and NMOS transistors for the cross-coupling pair, resulting in ultra-low-power consumption. Meanwhile, we add a higher-order resonator based on the transformer to compensate for the fatal defect: narrow locking range (LR) due to low power consumption. In the simulation results, when injection at 0-dBm, the LR can reach 1.8 GHz (21.2–23 GHz, 8.1%) with only 3.09–3.80 mW core-power consumption. And output is locked at 22 GHz when injection at 7.33 GHz with 10.13 dBc/Hz @ 1MHz phase noise (PN) deterioration.","PeriodicalId":163200,"journal":{"name":"2021 IEEE 3rd International Conference on Circuits and Systems (ICCS)","volume":"237 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE 3rd International Conference on Circuits and Systems (ICCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCS52645.2021.9697180","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
In this paper, an ultra-low-power injection-locked frequency tripler (ILFT) based on a current-reuse structure is proposed with SMIC 55-nm CMOS design kit. Different from the conventional structure with a cross-coupling pair of two NMOS transistors, a current-reuse structure is introduced, consisting of a single PMOS and NMOS transistors for the cross-coupling pair, resulting in ultra-low-power consumption. Meanwhile, we add a higher-order resonator based on the transformer to compensate for the fatal defect: narrow locking range (LR) due to low power consumption. In the simulation results, when injection at 0-dBm, the LR can reach 1.8 GHz (21.2–23 GHz, 8.1%) with only 3.09–3.80 mW core-power consumption. And output is locked at 22 GHz when injection at 7.33 GHz with 10.13 dBc/Hz @ 1MHz phase noise (PN) deterioration.