Instructions activating conditions for hardware-based auto-scheduling

Abstract

Nowadays, implementing hardware accelerators by hand-writing the RTL still leads to better quality of the results with respect to those obtained by automating the design process. Manually developing and maintaining hardware designs, however, is a complex, time-consuming and error prone task, making improvements in the automatic design flow definition a fervent ongoing research topic. The most common approach is based on a statically computed scheduling order. Supports for features such as dynamic scheduling or unbounded latency of operations and functional units have been proposed with some limitations. Instructions auto-scheduling is an alternative to overcome such restrictions, while facing those situations that need or take advantage of run-time adaptive reordering of the instructions. This paper focuses on how to improve the synthesis of hardware cores by increasing automatic parallelism exploitation. The proposed approach computes the set of conditions to be satisfied for each instruction to be executed as soon as possible, allowing run-time auto-scheduling. Representing such conditions as logic functions, the corresponding hardware implementation can be easily automated. Experimental results have shown an encouraging enhancement in terms of performance, with a limited increase of area.