Instructions activating conditions for hardware-based auto-scheduling

S. Lovergine, Fabrizio Ferrandi
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引用次数: 3

Abstract

Nowadays, implementing hardware accelerators by hand-writing the RTL still leads to better quality of the results with respect to those obtained by automating the design process. Manually developing and maintaining hardware designs, however, is a complex, time-consuming and error prone task, making improvements in the automatic design flow definition a fervent ongoing research topic. The most common approach is based on a statically computed scheduling order. Supports for features such as dynamic scheduling or unbounded latency of operations and functional units have been proposed with some limitations. Instructions auto-scheduling is an alternative to overcome such restrictions, while facing those situations that need or take advantage of run-time adaptive reordering of the instructions. This paper focuses on how to improve the synthesis of hardware cores by increasing automatic parallelism exploitation. The proposed approach computes the set of conditions to be satisfied for each instruction to be executed as soon as possible, allowing run-time auto-scheduling. Representing such conditions as logic functions, the corresponding hardware implementation can be easily automated. Experimental results have shown an encouraging enhancement in terms of performance, with a limited increase of area.
激活基于硬件的自动调度条件的指令
如今,通过手写RTL实现硬件加速器仍然比通过自动化设计过程获得的结果质量更好。然而,手工开发和维护硬件设计是一项复杂、耗时且容易出错的任务,因此改进自动设计流程定义是一个热门的研究课题。最常见的方法是基于静态计算的调度顺序。对动态调度或操作和功能单元的无界延迟等特性的支持已经提出,但有一些限制。指令自动调度是克服这类限制的一种替代方法,当面对那些需要或利用运行时自适应指令重新排序的情况时。本文主要研究如何通过增加自动并行性开发来提高硬件核的综合性能。所提出的方法计算要尽快执行的每条指令需要满足的一组条件,从而允许运行时自动调度。将这些条件表示为逻辑函数,相应的硬件实现可以很容易地自动化。实验结果表明,在性能方面有了令人鼓舞的提高,但面积增加有限。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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