Ishmael Sameen, Yoong Choon Chang, N. Song, B. Goi, Chee Siong Lee
{"title":"Design space exploration of a 2-D DWT system architecture","authors":"Ishmael Sameen, Yoong Choon Chang, N. Song, B. Goi, Chee Siong Lee","doi":"10.1109/ICCIS.2010.5518584","DOIUrl":null,"url":null,"abstract":"This paper proposes a programmable 2-D DWT system architecture designed for the JPEG-2000 standard. The proposed system architecture, derived from an iterative design space exploration process using Altera's C2H compiler, provides a significant performance acceleration of 2-D DWT when compared to an optimized 2-D DWT software implementation and is capable of real-time video processing performance up to 720p (1280 × 720) image resolutions when synthesized and tested on an Altera DE3 Stratix III FPGA board.","PeriodicalId":445473,"journal":{"name":"2010 IEEE Conference on Cybernetics and Intelligent Systems","volume":"226 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE Conference on Cybernetics and Intelligent Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCIS.2010.5518584","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper proposes a programmable 2-D DWT system architecture designed for the JPEG-2000 standard. The proposed system architecture, derived from an iterative design space exploration process using Altera's C2H compiler, provides a significant performance acceleration of 2-D DWT when compared to an optimized 2-D DWT software implementation and is capable of real-time video processing performance up to 720p (1280 × 720) image resolutions when synthesized and tested on an Altera DE3 Stratix III FPGA board.