Extraction of open-via defects from industrial designs

Abstract

As shown by previous studies, shorts and opens should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools targeting the extraction of these defects focused only on the bridging faults in order to generate test patterns or to use this information for a precise fault diagnosis. However, for open defects there is no available commercial tool that performs the extraction of this defect. In this paper, we present a novel algorithm to extract the location of potential open defects caused by defective vias. This information is used to generate a subnet list containing the name of disconnected segments by each defective via. Experiments on real industrial designs show the algorithm's performance. The method proposed in this paper is supported by a design flow implementing existing commercial CAD tools.