Sheet and line resistance of patterned SOI surface film CD reference materials as a function of substrate bias

Abstract

Recently, NIST has been developing electrical test structures to serve as critical dimension (CD) reference artifacts for calibration of CD metrology systems. The reference artifacts are fabricated in monocrystalline silicon-on-insulator films and are responsive to the goals of the National Technology Roadmap for Semiconductors beyond the 120 nm generation. The features on these reference artifacts are produced with lattice-plane specific etch techniques which give vertical, atomically planar sidewalls and uniform conductivity. The electrical linewidths, or electrical CDs (ECDs), of these features are determined from the sheet resistance and the resistance of the feature. This paper reports on measurements and models of how the resistance per unit length changes as a function of substrate bias, providing a method to validate the calculated sheet resistance and linewidth, and thus facilitating the use of this uniquely high repeatability and low-cost metrology tool in the production of CD-reference artifacts.