{"title":"Analysis and design of fully integrated very low quiescent current LDOs","authors":"Harish Valapala, P. Furth","doi":"10.1109/MWSCAS.2012.6291999","DOIUrl":null,"url":null,"abstract":"We introduce two extremely low quiescent current (I<sub>Q</sub>) low-dropout (LDO) voltage regulators. The Low I<sub>Q</sub>-LDO (LI<sub>Q</sub>-LDO) has a minimum ground current of 13 μA and is designed for a maximum load current of 50 mA. The Micro I<sub>Q</sub>-LDO (MI<sub>Q</sub>-LDO) has a minimum ground current of 1.2 μA and is designed for a maximum load current of 5 mA. Detailed pole/zero analysis is performed to aid in the design of the LDOs. Two LHP zeros cancel the two non-dominant poles which extend the bandwidth and improve transient response. Both designs are fully integrated, stabilized with an on-chip capacitive load of 100 pF. A process-independent figure of merit (FOM) is proposed to compare LI<sub>Q</sub>-LDO and MI<sub>Q</sub>-LDO with other published work.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2012.6291999","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
We introduce two extremely low quiescent current (IQ) low-dropout (LDO) voltage regulators. The Low IQ-LDO (LIQ-LDO) has a minimum ground current of 13 μA and is designed for a maximum load current of 50 mA. The Micro IQ-LDO (MIQ-LDO) has a minimum ground current of 1.2 μA and is designed for a maximum load current of 5 mA. Detailed pole/zero analysis is performed to aid in the design of the LDOs. Two LHP zeros cancel the two non-dominant poles which extend the bandwidth and improve transient response. Both designs are fully integrated, stabilized with an on-chip capacitive load of 100 pF. A process-independent figure of merit (FOM) is proposed to compare LIQ-LDO and MIQ-LDO with other published work.