Analysis and design of fully integrated very low quiescent current LDOs

Harish Valapala, P. Furth
{"title":"Analysis and design of fully integrated very low quiescent current LDOs","authors":"Harish Valapala, P. Furth","doi":"10.1109/MWSCAS.2012.6291999","DOIUrl":null,"url":null,"abstract":"We introduce two extremely low quiescent current (I<sub>Q</sub>) low-dropout (LDO) voltage regulators. The Low I<sub>Q</sub>-LDO (LI<sub>Q</sub>-LDO) has a minimum ground current of 13 μA and is designed for a maximum load current of 50 mA. The Micro I<sub>Q</sub>-LDO (MI<sub>Q</sub>-LDO) has a minimum ground current of 1.2 μA and is designed for a maximum load current of 5 mA. Detailed pole/zero analysis is performed to aid in the design of the LDOs. Two LHP zeros cancel the two non-dominant poles which extend the bandwidth and improve transient response. Both designs are fully integrated, stabilized with an on-chip capacitive load of 100 pF. A process-independent figure of merit (FOM) is proposed to compare LI<sub>Q</sub>-LDO and MI<sub>Q</sub>-LDO with other published work.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2012.6291999","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

Abstract

We introduce two extremely low quiescent current (IQ) low-dropout (LDO) voltage regulators. The Low IQ-LDO (LIQ-LDO) has a minimum ground current of 13 μA and is designed for a maximum load current of 50 mA. The Micro IQ-LDO (MIQ-LDO) has a minimum ground current of 1.2 μA and is designed for a maximum load current of 5 mA. Detailed pole/zero analysis is performed to aid in the design of the LDOs. Two LHP zeros cancel the two non-dominant poles which extend the bandwidth and improve transient response. Both designs are fully integrated, stabilized with an on-chip capacitive load of 100 pF. A process-independent figure of merit (FOM) is proposed to compare LIQ-LDO and MIQ-LDO with other published work.
全集成极低静态电流ldo的分析与设计
我们介绍了两种极低静态电流(IQ)低压差(LDO)稳压器。Low IQ-LDO (LIQ-LDO)最小接地电流为13 μA,最大负载电流为50 mA。Micro IQ-LDO (MIQ-LDO)的最小接地电流为1.2 μA,最大负载电流为5 mA。进行了详细的极/零分析,以帮助ldo的设计。两个LHP零抵消了两个非主导极点,从而延长了带宽并改善了瞬态响应。这两种设计都是完全集成的,并且片上电容负载为100pf。提出了一个与工艺无关的品质系数(FOM)来比较LIQ-LDO和MIQ-LDO与其他已发表的工作。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信