Switched-Capacitor Based Buck Converter Design Using Current Limiter for Better Efficiency and Output Ripple

Tamal Das, P. Mandal
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引用次数: 11

Abstract

In this paper we are addressing power efficiency and output ripple of an embedded switched-capacitor based DC/DC Buck Converters. Here we propose to use current pump based switched-capacitor circuit in buck converter. The current pump circuit limits transition current of the switched-capacitors and hence, improves power efficiency and reduces output ripple. We have also proposed an equivalent macro model of this type of current pump based switched-capacitor converter which would help to get a better essence of the closed loop stability of the system and would reveal clearly trade-offs among load current,  flying capacitance and clock frequency. A transistor level implementation of the proposed buck converter in 0.18µ technology is provided. For a load current of 8mA (maximum)the achieved power efficiency is 72.7% and the output ripple is 27mV. The flying capacitors in the converter are 2x108pF and the load capacitor is 125pF.
利用限流器设计基于开关电容的降压变换器以提高效率和输出纹波
本文研究了一种基于开关电容的嵌入式DC/DC降压变换器的功率效率和输出纹波。本文提出在降压变换器中采用基于电流泵的开关电容电路。电流泵浦电路限制了开关电容器的转换电流,从而提高了功率效率并减少了输出纹波。我们还提出了这类基于电流泵的开关电容变换器的等效宏观模型,这将有助于更好地了解系统闭环稳定性的本质,并将清楚地揭示负载电流,飞行电容和时钟频率之间的权衡。给出了采用0.18µ技术的降压变换器的晶体管级实现。负载电流为8mA(最大值)时,实现的功率效率为72.7%,输出纹波为27mV。变换器中的飞行电容为2x108pF,负载电容为125pF。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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