Cache-resident self-testing for I/O circuitry

Abstract

A technique is described for testing the I/O interfaces of a microprocessor through the use of cache-resident self-test. Experimental results show that this test application method executes much faster than traditional scan-based testing for both characterization and production versions of the tests. The addition of on-chip post-processing of test results further enhances the speedup. The method is compatible with low-cost testers.