23.1 An 8Gb 12Gb/s/pin GDDR5X DRAM for cost-effective high-performance applications

Abstract

Over the last years, GDDR5 has emerged as the dominant standard for applications requiring high system bandwidth like graphic cards and game consoles. However, GDDR5 data rates are saturating due to limitations in the clock frequency and column-access cycle time (tCCD). To reach the data rate of 9Gb/s/pin [1], a GDDR5 DRAM has to be clocked at 2.25GHz and operate at a tCCD of 888ps. This combination makes the design of control logic, data path and memory core difficult in a typical DRAM process. Still, the industry is demanding higher system bandwidth to enable continuous improvements in the visual computing arena. For this purpose, an 8Gb GDDR5X DRAM has been developed reaching a data rate of 12Gb/s/pin, which surpasses the fastest published GDDR5 [1] by 33%. This paper introduces GDDR5X and discusses relevant circuit techniques in clock generation, receiver and transmitter design to enable the higher data rates on a conventional DRAM process.