Design of Balanced Ternary Encoder and Decoder

Abstract

The origin of Ternary computing which is based on a 3-valued logic, can be traced back to the 18th century. Despite having its enormous potential to deal with a huge range of numbers with low consumption of power, Ternary logic system has received little attention with the advent and unprecedented progress of binary computers. In this paper, we propose an architecture and design of Balanced Ternary Encoder and Decoder circuit. The existing Encoder and Decoder circuits uses Unbalanced Ternary to create desired functions and are limited to only two logic levels, whereas the proposed Encoder and Decoder circuits harnessing the property of Balanced Ternary, exploit all the possible logic levels and can be used in both Balanced Ternary and Binary Coded Balanced Ternary applications. The complexity of the circuits is calculated to show the potential of proposed designs.