A Current-Attenuator for Performing Read Operation in Memristor-Based Spiking Neural Networks

Abstract

This paper presents a current attenuator fabricated in a CMOS 180nm technology, which works based on a CMOS ladder scheme. The attenuation factor is 104.14 dB, while it shows a non-linearity feature of less than 1.8 %. The circuit occupies an area of 2448 µm2. Since the output current could be as low as tens of femtoamperes, an on-chip testing circuit is also proposed to make the lab-measurements as accurate as possible. The final results show that chip-measurements are following simulations. As a demonstrator, the current attenuator is internally connected to a compact CMOS neuron cell. The output membrane potential shows that the neuron is generating a real-time firing modality, and consequently approves that the current-attenuator is working robustly.