Low-latency power-efficient adaptive router design for network-on-chip

Abstract

Network-on-chip (NOC) technology has offered an efficient solution for scalability problem. Following the advent of the NOC technology, decreasing the static power consumption has been at the focus of research and development. Since the routers are the most important and main power-consuming modules of NOC, most of the contributions are related to improvement in router micro-architecture design [1], [2]. Power-gating is currently an effective solution in this area but it causes overhead in terms of delays and in some cases it deteriorates the performance. In this paper, a power efficient design for the network-on-chip (NOC) routers using adaptive routing has been proposed. The Proposed scheme is directing the traffic in a power-gated network with respect to the routers status. In this way, we avoid to turn on the routers, that are in sleep state by alternating the paths. Our simulation has shown that we can achieve near 80% reduction in static power consumption compared to non-power-gated design and we improved the average delay by 35% in comparison with conventional power-gated design.