HLS Based Ultra-low Latency FAST Protocol Decoder

Abstract

Nowadays the advantages of heterogeneous acceleration technology are becoming more and more obvious. Edge computing center began to accelerate its distributed trading business based on FPGA technology, especially in the field of securities. Shanghai stock market uses efficient FIX Adapted for Streaming (FAST) protocol to transmit the market data. FAST protocol has high compression ratio and complex decoding process. Aiming at efficient FAST protocol decoding, we propose a new general FPGA logic design framework, which implements a low complexity parallel FAST field matching state machine and a low latency stock code mapping mechanism. In this paper, Vivado HLS is used to design and generate the relevant codes. Test results show that the clock frequency after place and routing can reach 250MHz under Xilinx VU37P FPGA. For the 10-level and 50-order message of FAST decoding, the processing delay of core parsing module is only 36ns and 56ns, FPGA subsystem delay is about 120ns. The solution in the paper is one order of magnitude more than traditional CPU software solutions, and is superior to other existing designs base on FPGA, so it is expected to be widely used in the financial market.