{"title":"Advanced Search Techniques for Circuit Partitioning","authors":"S. Areibi, A. Vannelli","doi":"10.1090/dimacs/016/03","DOIUrl":null,"url":null,"abstract":"Most real world problems especially circuit layout and VLSI design are too complex for any single processing technique to solve in isolation. Stochastic, adaptive and local search approaches have strengths and weaknesses and should be viewed not as competing models but as complimentary ones. This paper describes the application of a combined Tabu Search 1] and Genetic Algorithm heuristic to guide an eecient interchange algorithm to explore and exploit the solution space of a hypergraph partitioning problem. Results obtained indicate, that the generated solutions and running time of this hybrid are superior to results obtained from a combined eigenvector and node interchange method 11]. 1. Introduction In the combinatorial sense, the layout problem is a constrained optimization problem. We are given a description of a circuit (usually called a netlist) which is a description of switching elements and their connecting wires. We seek an assignment of geometric coordinates of the circuit components that satisses the requirements of the fabrication technology (suucient spacing between wires, restricted number of wiring layers, and so on), and that minimizes certain cost criteria. Practically all versions of the layout problem as a whole are intractable; that is, they are NP-hard. Thus, we have to resort to heuristic methods to attempt to solve such problems. One of these methods is to break up the problem into subproblems (circuit partitioning, component placement and wire routing).","PeriodicalId":376860,"journal":{"name":"Quadratic Assignment and Related Problems","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"30","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Quadratic Assignment and Related Problems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1090/dimacs/016/03","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 30
Abstract
Most real world problems especially circuit layout and VLSI design are too complex for any single processing technique to solve in isolation. Stochastic, adaptive and local search approaches have strengths and weaknesses and should be viewed not as competing models but as complimentary ones. This paper describes the application of a combined Tabu Search 1] and Genetic Algorithm heuristic to guide an eecient interchange algorithm to explore and exploit the solution space of a hypergraph partitioning problem. Results obtained indicate, that the generated solutions and running time of this hybrid are superior to results obtained from a combined eigenvector and node interchange method 11]. 1. Introduction In the combinatorial sense, the layout problem is a constrained optimization problem. We are given a description of a circuit (usually called a netlist) which is a description of switching elements and their connecting wires. We seek an assignment of geometric coordinates of the circuit components that satisses the requirements of the fabrication technology (suucient spacing between wires, restricted number of wiring layers, and so on), and that minimizes certain cost criteria. Practically all versions of the layout problem as a whole are intractable; that is, they are NP-hard. Thus, we have to resort to heuristic methods to attempt to solve such problems. One of these methods is to break up the problem into subproblems (circuit partitioning, component placement and wire routing).