Testing devices according to an architecture specification

Abstract

This paper describes methods for verifying and testing very large scale integrated (VLSI) electronic devices and subsystems according to an architecture specification. With these methods, the specification serves as the database which drives the verification and testing of the device through all phases of development: simulation, functional testing, and characterization. A hierarchical method of organization for an architecture specification is shown, verified, used to generate test cases for simulation and testing on a VLSI test system. Finally, methods for generating test programs and characterization tests are described. The unifying theme of these methods is that an architectural specification can be used to generate all phases of development.<>