{"title":"Multiple Clock Domain Design","authors":"Vaibbhav Taraate","doi":"10.1007/978-81-322-2791-5_13","DOIUrl":null,"url":null,"abstract":"","PeriodicalId":257254,"journal":{"name":"Digital Logic Design Using Verilog","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digital Logic Design Using Verilog","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1007/978-81-322-2791-5_13","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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