Leakage power optimization in standard-cell designs

Abstract

Leakage power consumption is a growing concern in integrated circuit design. Nanometer CMOS transistors are characterized by significant sub-threshold and gate leakage currents and feature size scaling is exacerbating this problem. In today's technologies (i.e., 90 nm), sub-threshold leakage currents are still dominant with respect to gate currents (although the trend shows that the latter grows more rapidly as technology scales). In this talk, we introduce a complete methodology for sub-threshold leakage current reduction based on the concept of sleep transistor insertion. Our insertion approach is layout-aware and it is fully compatible with industry-standard row-based layout styles and the supporting design tools. Sleep transistor cells are chosen from a library of cells that has been designed for high layout efficiency. These cells are inserted at the boundaries of existing cell rows, causing minimal disruption in placement and routing. The methodology ensures tight control of area and delay overheads, as it allows to selectively choose which gates in the netlist are connected to the sleep transistors. The effectiveness of the sleep transistor insertion methodology has been benchmarked on a set of design examples for which a physical implementation was obtained through commercial EDA tools; the results we have achieved show a reduction of leakage power ranging from 74% to 83%, depending on the circuit.