Analysis of analog parameters in NW-TFETs with Si and SiGe source composition at high temperatures

Abstract

In this work, the analysis of analog parameters in Tunnel-FET devices is performed at high temperatures and for two different source compositions (Si and Si_0.73Ge_0.27). For high gate voltage, band-to-band tunneling is the dominant mechanism, and due to that, a degradation in output conductance (g_D), early voltage (V_EA) and intrinsic voltage gain (A_V) was observed. In the SiGe devices, trap assisted tunneling is the dominant mechanism at low gate bias, which improves g_D, V_EA and consequently A_V. The temperature increases both I_ON and I_OFF current leading to a degradation of g_D, V_EA and A_V. The transistor efficiency (gm/I_D) decreases at high temperature in the “weak inversion region” and improves in the “strong inversion region” at high current.