The reduction of LSI chip costs by optimizing the alignment yields

Abstract

The area of an LSI chip depends not only on the minimum dimensions for the lines and spacings, but also on the realignment tolerances that are required in order to either assure or prevent an overlap for features on separate levels. Normal distributions are assumed for the misalignments and the feature sizes. A normalized solution is derived for the nominal size of each feature as a function of the alignment yield and of the standard deviations for misalignment and feature size. Applications and tradeoff examples are discussed. A simple cost model is examined in which it is shown that the larger the chip size the lower the alignment yields should be.