Junction Optimization for Embedded 40nm FN/FN Flash Memory

Abstract

2-transistor (2T) cell technology used for embedded non-volatile memory (eNVM) has been scaled down to 40nm node. To enable aggressive cell scaling, the array architecture is modified compared to previous generations and the channel length of cell is drastically reduced requiring steep cell junctions, which give rise to new disturb phenomena. This paper describes how to safeguard the drain disturb immunity in 40nm 2T eNVM, while maintaining the intrinsic 2T robustness.