Design of a Low Noise Low Power Amplifier for Biomedical Applications

Abstract

In this paper an ultra-low power two-stage amplifier for EEG signal amplifying is presented. A BulkDriven Folded Cascode structure is used. To reduce the flicker noise, PMOS input transistors with large gate areas and operating in sub-threshold region are used. The circuit is designed and simulated using the 0.18µm process, in the Analog Design Environment of Cadence Virtuoso. The performance of the circuit is studied at all process corners, namely TT, FF, FS and SF, along with Monte Carlo analysis. The amplifier achieving an open loop dc gain of 83.58dB, 7.7pV2/Hz input referred noise at 10Hz and power consumption of 0.351µW with 0.5V supply voltage and 35nA current source.