Minimization of NAND circuits by rewriting-rules heuristic

Abstract

A method is given for further minimizing the multilevel NAND gate circuit having single-rail inputs obtained by applying the inhibiting-loop method of K. Goto (1989) to the given function. Using several theorems proposed by the authors several rules are used to determine whether the same input exists in the preceding and succeeding gate levels, and to determine whether the common input exists at the same first level of some parallel multilevel NAND gates, or other conditions. The Lisp language program utilizing this method was run on the microVAX-II computer for three-variable P-equivalence classes and four-variable functions. As a result, the coincidences for the three-variable functions and four-variable functions between the ideal results and the obtained results were 40% and 11%, respectively, when using the inhibiting-loop method alone. However, the results improved to 90% and 64%, respectively, by the addition of this reducing method.<>