Design of High-performance SoC Simulation Model Based on Verilator

Abstract

With the development of Moore's Law, the design complexity of SoC is increasing, and the traditional simulation verification method has been unable to meet the rapid iteration of products. A high-performance SoC simulation model design scheme based on Verilator is proposed to improve the speed of SoC simulation verification and shorten the chip development and design cycle. Based on the ESL design method, Openc910 is selected as the starting point to design a high-performance SoC simulation model based on Verilator. The SM3 and SM4 crypto modules are designed in the SoC, and Iverilog simulation tool is used for comparison. Compared with using the traditional Iverilog simulation, the experimental results using Verilator show the effectiveness of the design.