Design optimization of tunnel FET for dynamic memory applications

Abstract

The work reports on an innovative design to improve the scalability of misaligned Double Gate (DG) Tunnel Field Effect Transistor (TFET) for operation as dynamic memory. The design optimization is achieved through use of lateral gap on both edges of back gate (G2) that reduces Band-to-Band Tunneling (BTBT) and enhances Retention Time (RT) by a factor of ∼3. The front gate responsible for read mechanism can be scaled down to 75 nm while G2 can be scaled until 40 nm. The investigation highlights better scalability and improved retention characteristics.