A robust histogram-based image segmentation ASIC design for System-on-Chip using 65nm technology

Abstract

Image segmentation is an essential preprocessing step for many computer vision and image processing applications. Implementing algorithms that handle such images in hardware will speed up the processing task considerably. In this paper, a new robust histogram-based image segmentation ASIC design of a System-on-Chip (SoC) using 65nm technology is presented. With a clock frequency of 289 MHz, the SoC can reach a frame rate of a 4410 FPS for an image resolution of 256×256. This is few order of magnitudes faster than the FPGA implementation in the literature. The finished-chip details renders it suitable for real-time and mobile applications.