Leakage power evaluation of FinFET-based FPGA cluster under threshold voltage variation

Abstract

The leakage power of FinFET-based FPGA cluster is studied and evaluated with technology node 14nm. The impact of threshold voltage variation, considering die-to-die variations, on the leakage power is reported after simulating a 2-Bit adder benchmark and comparing the results with the dynamic power consumption. Simulation results show, with the leakage power segmentation, that the multiplexers are the most consuming components for leakage power in the FPGA cluster architecture. Some leakage power control techniques are investigated including transistor stacking, minimum leakage vector, and gate sizing. The effect of each technique on the leakage power, leakage power variation, and the delay is reported and compared with the original design.