Programming Efficiency of Stacked-Gate Flash Memories with High-κ Dielectrics

2006 IEEE Conference on Emerging Technologies - Nanoelectronics Pub Date : 2006-03-27 DOI:10.1109/NANOEL.2006.1609734

Y. Chen, C. Chien, K. Kin, J. Lou

{"title":"Programming Efficiency of Stacked-Gate Flash Memories with High-κ Dielectrics","authors":"Y. Chen, C. Chien, K. Kin, J. Lou","doi":"10.1109/NANOEL.2006.1609734","DOIUrl":null,"url":null,"abstract":"The programming efficiency of high-permittivity (κ) inter-poly dielectrics (IPDs) and tunnel dielectrics (TDs) on the stacked-gate flash memory performance is evaluated. By 2D MEDICI simulation, stacked-gate flash memories with high-κ IPDs clearly exhibited significant improvement in operation speed over those with conventional oxide/nitride/oxide IPD programmed with either channel Fowler-Nordheim (CFN) or channel hot electron (CHE) injection. Choosing HfO2as the IPD and using CFN programming scheme, the operating voltage can be reduced by more than 48% under a typical 10μs programming time. However, the effect of high-κ TDs was quite different when compared with high-κ IPDs. High-κ TDs were only beneficial for memories programmed with CHE injection instead of CFN tunneling. The operating voltage can be reduced by more than 27% under 10μs programming time by choosing HfO2as both the IPD and TD with CHE programming scheme. Due to the contrary improvement in programming schemes, high-κ IPDs and TDs were suitable for next-generation NAND- and NOR-type stacked-gate flash memories, respectively.","PeriodicalId":220722,"journal":{"name":"2006 IEEE Conference on Emerging Technologies - Nanoelectronics","volume":"108 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE Conference on Emerging Technologies - Nanoelectronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NANOEL.2006.1609734","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

Abstract

The programming efficiency of high-permittivity (κ) inter-poly dielectrics (IPDs) and tunnel dielectrics (TDs) on the stacked-gate flash memory performance is evaluated. By 2D MEDICI simulation, stacked-gate flash memories with high-κ IPDs clearly exhibited significant improvement in operation speed over those with conventional oxide/nitride/oxide IPD programmed with either channel Fowler-Nordheim (CFN) or channel hot electron (CHE) injection. Choosing HfO2as the IPD and using CFN programming scheme, the operating voltage can be reduced by more than 48% under a typical 10μs programming time. However, the effect of high-κ TDs was quite different when compared with high-κ IPDs. High-κ TDs were only beneficial for memories programmed with CHE injection instead of CFN tunneling. The operating voltage can be reduced by more than 27% under 10μs programming time by choosing HfO2as both the IPD and TD with CHE programming scheme. Due to the contrary improvement in programming schemes, high-κ IPDs and TDs were suitable for next-generation NAND- and NOR-type stacked-gate flash memories, respectively.

查看原文本刊更多论文

高- 954堆叠门闪存的编程效率电介质

研究了高介电常数(κ)多间电介质(IPDs)和隧道电介质(td)的编程效率对堆叠栅极闪存性能的影响。通过二维MEDICI模拟，具有高κ IPD的堆叠栅极闪存的运行速度明显优于具有传统氧化物/氮化物/氧化物IPD的堆叠栅极闪存，这些IPD分别由通道富勒-诺德海姆(CFN)或通道热电子(CHE)注入编程。选择hfo2作为IPD，采用CFN编程方案，在典型的10μs编程时间下，工作电压可降低48%以上。然而，与高κ IPDs相比，高κ TDs的作用有很大差异。高κ td只对CHE注入编程的记忆有益，而对CFN隧道没有作用。采用CHE编程方案，选择hfo2作为IPD和TD，在10μs编程时间内，工作电压降低27%以上。由于编程方案的相反改进，高κ ipd和TDs分别适用于下一代NAND和no型堆叠门闪存。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

2006 IEEE Conference on Emerging Technologies - Nanoelectronics

自引率

0.00%

发文量