Time Sharing Based Parallel Implementation of CNN on Low Cost FPGA

Abstract

Convolutional neural network (CNN) is a multilayer architecture, and considered as a robust model for image recognition. Learning in this neural network achieves progressively in its successive layers such that the layers produce higher-level features and the categories are produced by the last layer. To use the CNN in different real time applications, high performance implementation is required. To reduce the resources required for implementation, in this paper a time sharing based parallel implementation of CNN is proposed. The computing of the upper convolution nodes is done sequentially while the parallelism is increased in the direction of the preceding layer resulting maximum parallelism in the bottom layer Then the CNN relatively complex design is implemented on an FPGA model with no more than 200,000 gates and can speed up computation up to 166 times.